ASIC/FPGA Timing Questions

1.  Is there any possibility of getting setup and hold violations in the same path ,if so how is it possible?
• In case of high frequency timing constraints
2. What is propagation delay?
• All devices have some delay associated with transferring an input change to the output. These changes are not immediate in a real environment. This delay that is due to the signal propagation through the device is called the propagation delay. 
3. What is Setup time?
• Setup time is the amount of time that an input signal (to the device) must be stable (unchanging) before the clock ticks in order to guarantee minimum pulse width and thus avoid possible meta-stability.
4. What is Hold time?
• Hold time is the amount of time that an input signal (to a sequential device) must be stable (unchanging) after the clock tick in order to guarantee minimum pulse width and thus avoid possible meta-stability.
5. What all the different types of clock skews
• Positive skew:  If capture clock comes late than launch clock then it is called positive skew.
• Negative skew : If capture clock comes early than launch clock it is called –ve skew.
• Useful Skew :  If clock is skewed intentionally to resolve violations, it is called useful skew
6. What is Recovery time? 
• Is like setup time on a reset pin.
7. Removal time? 
• Is like hold time on a reset pin
8. Does Clock gates also have setup hold requirements?
• Yes
9. Clock Domain Crossing issues are not detected by Static Timing Analysis(STA)
10. How setup and hold violations affects the ASIC chip?
• If a chip is done with some setup time violations; chip can make it work by reducing the desired frequency
• If a chip is done with hold violations, JUST DUMP the chip. This is how it effects at the end of the day. Hold violations needs to be fixed at any cost.
11. What changes need to be done to fix hold violations and make DESIGN work?
• Place and route tools will place and route the cells in such a way that no timing violations will occur.
• If still hold violations remained, then we can  manually place the cells to avoid hold violations . 
• We can keep some buffers in the data path to avoid hold violations (but be sure setup timing is not effected.) 
• We can delay the source clock path keeping destination clock as it is (but be sure destination has enough setup time)
12. Setup Clock skew = Destination (min) – Source (max)
• This is always negative clock skew. Lesser the value then worse will be the setup time
13. Hold Clock skew = Source (max) – Destination (min)
• This is always Positive clock skew. Greater the value then worse will be the hold time
14. Talk about floor planning
• Floor planning is the process of choosing the best grouping and connectivity of logic in a design, and of manually placing blocks of logic in an FPGA, where the goal is to increase density, routability, or performance.
• Floor planning is a technique that can be used to reduce the amount of route delay in a critical path. You can identify logic that is contributing to timing problems and guide the place and route tools to keep the logic close together. The end goal is to improve the timing of the critical paths by reducing the amount of routing delay. A good floor planning methodology can improve performance and help the placed and routed design meet timing.

More questions will be added soon...