RTL design Questions

1. Which kind of encoding is preferred in FPGA?
• One hot coding... Since the Xilinx/Altera/Actel FPGA's have intensive flip flops in them.
• One hot encoding is the fastest encoding method
2. Tell us about preferred way of FSM encoding in CPLD and FPGA?
• Typically, Moore style, one-hot state-machines implement better for FPGAs
• Mealy, binary state-machines implement best for CPLDs.
3. Make an INVERTER using only two input NAND gate 
4. Make an INVERTER using only two input NOR gate 
5. How do you know, if given circuit, whether it is a combinational Circuit or a sequential circuit?
   
   • If a circuit has only combinational devices (e.g.. gates like AND, OR etc and MUX(s))and no Memory elements then it is a Combinational circuit. If the circuit has memory elements such as Flip Flops, Registers, Counters, or other state devices then it is a Sequential Circuit.  Synchronous sequential circuits will also have a clearly labeled clock input.
6. What's the difference between a latch and a flip-flop? Write Verilog RTL code for each 
• Latch is a level triggered device and flip flop is a edge triggered device.
• When a latch is enabled it becomes transparent while a flip flop's output only there is changes(posedge/negedge) on the clock edge
• Latches are built from logic gates and whereas FF's can be built from the latches
7. What are glitches? How to eliminate them?

• You can use low pass filter in analogue land(domain). A minimum width threshold (glitch detector) is a useful block to have in digital land, especially if your minimum width is tied to registers (not hardwired); you can then tune the glitch rejection if need be.
• A combination of both is even better.
• Note if you have a very short asynchronous pulse and want to register that to internal logic, the likelihood is you'll get some occasional wierd effects in the digital domain, perhaps missing some pulses altogether. Chain several FFs together, all clocked with global clock of course, even as many as 6-8 FFs, to have a better chance of getting a clean input.

1.       8. How to solve the glitch of digital circuit??      

Glitch can be smoothened by the using a capacitor from the supply to the ground

(0.01µ and 0.1µ are the commonly used values.....)

9. what is difference between RAM and FIFO? 

FIFO does not have address lines; RAM is used for storage purpose where as fifo is used for synchronization purpose i.e. when two peripherals are working in different clock domains then we will go for fifo.



Design a FIFO 


A synchronous FIFO is a FIFO where the same clock is used for both reading and writing.
An asynchronous FIFO uses different clocks for reading and writing.

Asynchronous FIFOs introduce metastability (it means that it has equilibrium) issues. A common implementation of an asynchronous FIFO uses a Gray code (or any unit distance code) for the read and write pointers to ensure reliable flag generation. One further note concerning flag generation is that one must necessarily use pointer arithmetic to generate flags for asynchronous FIFO implementations. Conversely, one may use either a "leaky bucket" approach or pointer arithmetic to generate flags in synchronous FIFO implementations.

Asynchronous FIFOs required read and write pulses to be generated as data is
moved through the part, and generating these pulses is difficult to do at high speed

Application: It is normally used in network components such as routers, switches, etc. and in electronic circuitry that we use on daily basis such as TVS, radios, MP3 players, etc. As to why not use an ordinary buffer is just not as efficient for today's and future applications.


Synchronous FIFOs have quickly become the FIFOs of choice for new designs. This movement to synchronous FIFOs from their asynchronous predecessors is due mainly to speed and ease of operation. However, there are also many other advantages which these devices bring such as
synchronous flags, programmable almost empty and almost full flags, depth expansion, and retransmit. Synchronous FIFOs are easier to use at high speeds since they can be operated by free running clocks.

In many board to board communication schemes, error checking is done to insure proper transmission. Synchronous FIFOs have a retransmit feature which allows the board which
is sending the data to re-send or “retransmit” the data when an error occurs. Another popular use for FIFOs is interprocessor communication. Often processors run at different bus rates, so passing data through a FIFO allows each processor to burst data into and out of the FIFO at their maximum speeds. FIFOs have no address lines, which saves pin count and therefore board space. Because of this, FIFOs are often used to buffer sequential data such as video or voice. Telecommunication and datacommunication information possesses this sequential ordering as well. Often FIFOs are used on the front end of each network port to synchronize incoming network
packets.

Different duty cycle clock generation
Hold and setup violation condition

Q2: What kinds of timing violations are in a typical timing analysis report? Explain!
Ans: Acceptable answers...
- Setup time violations
- Hold time violations
- Minimum delay
- Maximum delay
- Slack
- External delay

Q3: List the possible techniques to fix a timing violation.
Ans: Acceptable answers...
- Buffering
- Wire sizing
- Transistor sizing
- Re-routing
- Placement updates
- Re-synthesis (logic transformations)
- Cloning
- Taking advantage of useful skew
- Making sure we don't have false violations (false path, etc.)

Blocking and Non-blocking: The Verilog language has two forms of the procedural assignment statement: blocking and non-blocking. The two are distinguished by the = and <= assignment operators. The blocking assignment statement (= operator) acts much like in traditional programming languages. The whole statement is done before control passes on to the next statement. The non-blocking (<= operator) evaluates all the right-hand sides for the current time unit and assigns the left-hand sides at the end of the time unit.


// Section 1: Blocking statements execute sequentially
#5 a = b;  // waits 5 time units, evaluates and applies value to a
   c = d;  // evaluates and applies value to c

// Section 2: Non-Blocking statements execute concurrently
#5 a <= b; // waits 5 time units, evaluates, schedules apply for end of current time
   c <= d; // evaluate, schedules apply for end of current time
           // At end of current time both a and c receive their values

How the following verilog code is synthesized???


reg sel, a;
always @ (sel, a)
  begin : latching_if
    if (sel == 1)
      f = a;
  end
Incomplete Assignment : Now analyze the behaviour of the code. If sel is 1, f gets a. But what happens when sel is 0? Well, very simply, nothing! f does not and can not change. When sel is fixed at 0, we can change a as much as we like, f will not be assigned the value of a. If we suppose that an if statement synthesises to a multiplexer, then we must be able to configure the multiplexer such that f only gets the value of a when sel is 1. This can be achieved by feeding back the multiplexer f output back to the 0 input; in hardware terms this is a transparent latch and this is exactly the hardware synthesized by a synthesis tool given this Verilog code.


If the target architecture does not contain transparent latches the synthesis tool will generate multiplexer circuits that employ combinational feedback in order to mimic the latching behaviour required.
Now, this is very well but what's really happening here? One minute if statements create multiplexers, the next they create latches. Well, it's not the if statements, but the process as a whole that counts. If it is possible to execute an always block without assigning a value to a signal in that always block, the reg variable will be implemented as a transparent latch. This is known as incomplete assignment.


divide by 3.5 clock divider

Divide by 3.5 clock divider

- Divide by 3 first and add the negedge flop in series to make divide by 3.5

A simple divide by 3 counter can be as as follows

=== Divide by 3 ===
always @ (posedge clk or negedge reset)
if (!reset) Q[1:0] <= 2'b0;
else Q[1:0] <= {Q[0], (!Q[1] & !Q[0])};

The above code is a sequence of 00, 01, 10, 00.

always @(negedge clk)
Q0_inv <= Q[0];

assign divide_by_3 = Q[0] | Q0_inv ;

====End of Divide by 3===

always @ (negedge clk)
divide_by_dot5 <= divide_by_3 ;

assign divide_by_3dot5 = divide_by_3 | divide_by_dot5;

===== End of Divide by 3.5====