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Sunday, November 29, 2015

FIFO Depth Calculation with more examples



FIFO Depth Calculation

FIFO depth calculation is very important in designing the asynchronous FIFO and depth calculation considers both overflow and underflow condition of the data. Wrong calculation of depth may lead to losing the data or adding unnecessary memory to the design.

Basically we use FIFO for synchronizing two clock domains (different frequencies) so we need a device which has some tolerance power to hold the data, that device is called FIFO. By using FIFO we can easily avoid overflow and underflow conditions.

The scenario can be two of following

·         Overflow : Writing is faster than reading
·         Underflow : Writing is slower than reading

Type I Method :

In FIFO depth calculation we always have to consider worst case size of FIFO basically implies that how much data is required to buffer. And it is totally depend on data rate of reading and writing.

DataRate(DR) = # of DataBits * TimePeriod
Difference = Fast DR – Slow DR
Depth = Difference/ (Higher DR Time Period)

Writing side is Source and Reading Side is Sink.

Type II Method :

D is the FIFO depth.

D = B * [1 - (Fread/Fwrite*RD)]
Where,
Fwrite = Clock Frequency of Write Clock Domain
Fread = Clock Frequency of Read Clock Domain
D = Depth or number of locations in FIFO to store.

B = Burst Width, number of words to store before idle time
RD = Read side delay in-between reads

Following are some cases of FIFO depth calculation with clear explanation

Case: 1
Writing Side = 30 MHz => 33.33 ns Time Period
Reading Side = 40 MHz = > 25.0 ns Time Period
Solution:
Consider the data size is = 10bit
Data Rate of Writing = 10 x (1/30) =333.33 ns
Data Rate of Reading = 10 x (1/40) =250.0 ns.
Difference between Data Rates = 333.33 – 250.0 = 83.33
Now divide with highest frequency time period = 83.33/25ns = 3.3332 = 4 (Aprox)
Depth of FIFO Should be 4

Case: 2
Writing Side = 80 Data/100 Clock = 100 MHz => 10ns Time Period
Reading Side = 80 Data/80 Clock = 80 MHz => 12ns Time Period
No Randomization
Solution:
Data Size is = 80
Data Rate of Writing =80*10=800ns
Data Rate of Reading=80*12=960ns
Difference = 960-800=160ns
Now divide with highest frequency time period = 160/10ns=16
            Depth of FIFO Should be 16

Case: 3
Writing Side = 80 Data/100 Clock = 200 MHz => 5ns Time Period
Reading Side = 80 Data/80 Clock = 100 MHz => 10ns Time Period
No Randomization
Solution:
Data Size is = 80
Minimum Time required to Write the data = 80*5   = 400ns
Maximum Time required to read the data   = 80*10 = 800ns
Difference = 800-400=400ns
Now divide with highest frequency time period = 400/5ns=80
Depth of FIFO Should be 80


Case: 4
Writing Side = 10 MHz => 100 ns
Reading Side = 2.5 MHz=>400 ns
Word Size = 2
Solution:
Data Rate of Writing =100*2=200ns
Data Rate of Reading=400*2=800ns
Difference = 800-200=600
            Now Divide by the lowest frequency time period = 600/400 = 1.5 = 2

Case: 5
Writing Side = 80 words in 100 clocks
Reading Side = 8 words in 10 clocks

Solution:
Worst scenario of overflow of data is when there is 160 clocks of continuous write.
Lets assume first 20 cycle is idle and then 80 clock cycle writing. Other set of writing starts at 101 clock cycle.
Worst scenario : 160 words are written in 160 clocks
Reading possibility : 8*16 = 128 words can be read
So depth of FIFO : 160-128 = 32


Case: 6

Write side of FIFO:
Write clock frequency = 15 MHz (clk_wr)
Maximum size of the Burst = 100 bytes (burst_width)
Delay between writes in a burst = 1 clock cycle (wr_delay)

Read side of FIFO
Read clock Frequency = 10 MHz (clk_read)
Delay between reads = 2 clock cycles (rd_delay)


Six step approach to calculate FIFO parameters.
Step1:- FIFO Width = 8 (1 byte = 8 bits worth of data at each buffer location)
Step2:- Assume depth of FIFO to capture the complete buffer = 100 (maximum size of burst)
Step3:- No of write clock cycles for writing 100 locations in FIFO = 100 @ clk_wr
Step4:- Time taken to write 100 locations = 100/(15*10^6) = 6.67 us
Step5:- No of reads during 6.67 us = (6.67 us) * 10 * 10^6 = 66.7 @ clk_read (approx 67)
Step6:- No of dead cycles between reads = 2
Depth of the FIFO = 100 – 66.7/2 = 100 – 33.35 = 66.65 = 67

Case: 7

Assume that we have to design a FIFO with following requirements and We want to calculate minumum FIFO depth,

A synchronized fifo
Writing clock 30MHz - Fwrite = F1
Reading clock 40MHz - Fread = F2
Writing Burst Size - B
Case 1 : There is 1 idle clock cycle for reading side - I
Case 2 : There is 10 idle clock cycle for reading side - I
 
FIFO depth calculation = B - B *F2/(F1*I)

If if we have alternate read cycles i.e between two read cycle there is IDLE cycle.

FIFO depth calculation = B - B * F2/(F1*2)

In our present problem FIFO depth = B - B *40/(30*2)
= B(1-2/3)
= B/3

That means if our Burst amount of data is 10 , FIFO DEPTH = 10/3 = 3.333 = 4 (approximately)

If B = 20 FIFO depth = 20/3 = 6.6 = 7 or 8 (clocks are asynchronous)

If B = 30 FIFO depth = 30/3 = 10, 10+1 = 11 (clocks are asynchronous)

If 10 IDLE cycles between two read cycles .

FIFO DEPTH = B - B *F2/(F1*10) .
= B(1-4/30)
= B * 26 /30

If B = 20 FIFO depth = 20* (26/30) = 17.33 = 18 (clocks are asynchronous)

If B = 30 FIFO depth = 30* (26/30) = 26 (clocks are asynchronous)


8 comments:

  1. For the type II, it's more generic fomular is as follows:

    FIFO depth = Burst_Width*[1- (Fread/Fwrite)*(WrDelay + 1)/(RdDelay + 1)]. When both WrDelay and Rdelay = 0, that will be the same as Type II mentioned above.

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  2. your calc are wrong. For ex: in first case, FIFO depth = 1 is enough for the worst case as the read side is running at higher freq.

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  3. YOU ARE DOING WRONG CALCULATIONS YOUR READING RATE IS ALREADY FASTER THAN WRITING RATE

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  4. Case1 is wrong. Reading speed is already higher than the writing speed. Why do you even need to send the data in bursts? Data will be sent in bursts only when we require FIFO. This is to ensure that FIFO will not receive continuos data so that it won't overflow. Even if there is no FIFO depth it's fine as long as clocks are in phase. However we can't guarantee whether the clocks will be in phase or not because routing of long wires may cause excessive delay. Just to ensure that this delay won't cause any problem we put a FIFO depth=1 so that both the clocks will be in same phase.

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  5. I could not understand how write frequency is 100MHz in case-2 ? can anybody explain?

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  6. Consider
    Write clock freq Fw = 100MHz,
    Read Clock Freq Fr = 50MHz,
    Data Burst length = 120, and No idle cycles between write and read operations.
    *Write and Read data width is equal

    By above method, the fifo Depth required is 60.


    But, consider this
    1. To write one burst of data, time taken is 1200ns
    2. To read one burst of data, time taken is 2400ns

    @1200ns, first write burst is complete, and buffer is half read
    @1201ns, write cycle is starting to write the data on the fifo start position, but read clock is continuing to read from the buffer (1201&1202, data at 31 address is read from the fifo)
    .
    .
    .
    @2400ns, 2nd write burst is complete, but read clock has only read the first burst of data.
    @2401ns, 3rd write burst is starting, and read clock starting to read from the fifo(starting to read 2nd burst of write data).
    (it takes two cycles of write clock to read one data from fifo, since Fw/Fr = 2, so data is not read from fifo until 2402ns.

    This creates a problem because, until the first position of fifo is free, write clock can not write data on the fifo.


    In this case, how Fifo depth of 60 is sufficient.

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  7. Will i be able to generate idle clock pulses in the FIFO If required
    For eg, If Writing frequency is much lower than Reading frequency will i be able to generate idle cycles for reading

    ReplyDelete