ASIC/FPGA Timing Questions

1.  Is there any possibility of getting setup and hold violations in the same path ,if so how is it possible?
• In case of high frequency timing constraints
2. What is propagation delay?
• All devices have some delay associated with transferring an input change to the output. These changes are not immediate in a real environment. This delay that is due to the signal propagation through the device is called the propagation delay. 
3. What is Setup time?
• Setup time is the amount of time that an input signal (to the device) must be stable (unchanging) before the clock ticks in order to guarantee minimum pulse width and thus avoid possible meta-stability.
4. What is Hold time?
• Hold time is the amount of time that an input signal (to a sequential device) must be stable (unchanging) after the clock tick in order to guarantee minimum pulse width and thus avoid possible meta-stability.
5. What all the different types of clock skews
• Positive skew:  If capture clock comes late than launch clock then it is called positive skew.
• Negative skew : If capture clock comes early than launch clock it is called –ve skew.
• Useful Skew :  If clock is skewed intentionally to resolve violations, it is called useful skew
6. What is Recovery time? 
• Is like setup time on a reset pin.
7. Removal time? 
• Is like hold time on a reset pin
8. Does Clock gates also have setup hold requirements?
• Yes
9. Clock Domain Crossing issues are not detected by Static Timing Analysis(STA)
10. How setup and hold violations affects the ASIC chip?
• If a chip is done with some setup time violations; chip can make it work by reducing the desired frequency
• If a chip is done with hold violations, JUST DUMP the chip. This is how it effects at the end of the day. Hold violations needs to be fixed at any cost.
11. What changes need to be done to fix hold violations and make DESIGN work?
• Place and route tools will place and route the cells in such a way that no timing violations will occur.
• If still hold violations remained, then we can  manually place the cells to avoid hold violations . 
• We can keep some buffers in the data path to avoid hold violations (but be sure setup timing is not effected.) 
• We can delay the source clock path keeping destination clock as it is (but be sure destination has enough setup time)
12. Setup Clock skew = Destination (min) – Source (max)
• This is always negative clock skew. Lesser the value then worse will be the setup time
13. Hold Clock skew = Source (max) – Destination (min)
• This is always Positive clock skew. Greater the value then worse will be the hold time
14. Talk about floor planning
• Floor planning is the process of choosing the best grouping and connectivity of logic in a design, and of manually placing blocks of logic in an FPGA, where the goal is to increase density, routability, or performance.
• Floor planning is a technique that can be used to reduce the amount of route delay in a critical path. You can identify logic that is contributing to timing problems and guide the place and route tools to keep the logic close together. The end goal is to improve the timing of the critical paths by reducing the amount of routing delay. A good floor planning methodology can improve performance and help the placed and routed design meet timing.

More questions will be added soon...

Reset myths

1. Why Reset?

• A Reset is required to initialize a hardware design for system operation and to force an ASIC into a known state for simulation. A reset simply changes the state of the device/design/ASIC to a user/designer defined state. 
• There are two types of reset, Synchronous reset and Asynchronous reset.

    2.    Why generally active low reset will be used?

• False start: When the power to a chip is turned on, we need FFs and certain critical circuits like program counters, memories start from default "reset" values. If these circuits are to be kept in reset state & the reset signal is active high, there will be sometime (few microseconds) before this signal reaches logic "1". This is because the power supply itself is ramping up to Vdd from logic "0". And the logic "0" is when the chip start functioning actively. So in a sense we are starting from functional mode to reset mode even though the chip is in the functional mode just few nano or microseconds. This may cause data corruption during the short time when reset was low before ramping to "high" inside critical circuit elements. Added to this is noise. As a result the chip may not boot up properly.

• Faster : Grounding the reset signal is faster and easier rather than waiting for it to go high to reset all circuits and then low to start the chip operations. 

3. What is the difference between synchronous reset and asynchronous reset?
   
   Synchronous Reset
   

• Advantages:
• The advantage  to this type of topology is that the reset presented to all functional flip-flops is fully synchronous to the clock and will always meet the reset recovery time.
• Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant.
• Synchronous resets provide some filtering for the reset signal such that it is not effected by glitches, unless they occur right at the clock edge. A synchronous reset is recommended for some types of designs where the reset is generated by a set of internal conditions. As the clock will filter the logic equation glitches between clock edges. 
• Disadvantages:

• The problem in this topology is with reset assertion. If the reset signal is not long enough to be captured at active clock edge (or the clock may be slow to capture the reset signal), it will result in failure of assertion. In such case the design needs a pulse stretcher to guarantee that a reset pulse is wide enough to be present during the active clock edge.
• Another problem with synchronous resets is that the logic synthesis cannot easily distinguish the reset signal from any other data signal. So proper care has to be taken with logic synthesis, else the reset signal may take the fastest path to the flip-flop input there by making worst case timing hard to meet.
• In some power saving designs the clock is gated. Synchronous reset will not take into effect unless there is active edge and if clock enable is off, there is no active edge of the clock. Designers has to carefully account this case and design reset and clock enabling strategy which account for proper design function.
• Faster designs that are demanding low data path timing, can not afford to have extra gates and additional net delays in the data path due to logic inserted to handle synchronous resets.
• Use of tri-state buffers post the synchronous flop and they need to be disabled at power up otherwise excessive current could pass into tr-state buffers and resulting in chip damage.

Asynchronous Reset

An asynchronous reset will affect or reset the state of the flip-flop asynchronously i.e. no matter what the clock signal is. This is considered as high priority signal and system reset happens as soon as the reset assertion is detected.

• Advantages:
• High speeds can be achieved, as the data path is independent of reset signal.
• Another advantage favoring asynchronous resets is that the circuit can be reset with or without a clock present.
• As in synchronous reset, no work around is required for logic synthesis.
• Disadvantages:

• The problem with this type of reset occurs at logic de-assertion rather than at assertion like in synchronous circuits. If the asynchronous reset is released (reset release or reset removal) at or near the active clock edge of a flip-flop, the output of the flip-flop could go metastable.
• Spurious resets can happen due to reset signal glitches.

RTL design Questions

1. Which kind of encoding is preferred in FPGA?
• One hot coding... Since the Xilinx/Altera/Actel FPGA's have intensive flip flops in them.
• One hot encoding is the fastest encoding method
2. Tell us about preferred way of FSM encoding in CPLD and FPGA?
• Typically, Moore style, one-hot state-machines implement better for FPGAs
• Mealy, binary state-machines implement best for CPLDs.
3. Make an INVERTER using only two input NAND gate 
4. Make an INVERTER using only two input NOR gate 
5. How do you know, if given circuit, whether it is a combinational Circuit or a sequential circuit?
   
   • If a circuit has only combinational devices (e.g.. gates like AND, OR etc and MUX(s))and no Memory elements then it is a Combinational circuit. If the circuit has memory elements such as Flip Flops, Registers, Counters, or other state devices then it is a Sequential Circuit.  Synchronous sequential circuits will also have a clearly labeled clock input.
6. What's the difference between a latch and a flip-flop? Write Verilog RTL code for each 
• Latch is a level triggered device and flip flop is a edge triggered device.
• When a latch is enabled it becomes transparent while a flip flop's output only there is changes(posedge/negedge) on the clock edge
• Latches are built from logic gates and whereas FF's can be built from the latches
7. What are glitches? How to eliminate them?

• You can use low pass filter in analogue land(domain). A minimum width threshold (glitch detector) is a useful block to have in digital land, especially if your minimum width is tied to registers (not hardwired); you can then tune the glitch rejection if need be.
• A combination of both is even better.
• Note if you have a very short asynchronous pulse and want to register that to internal logic, the likelihood is you'll get some occasional wierd effects in the digital domain, perhaps missing some pulses altogether. Chain several FFs together, all clocked with global clock of course, even as many as 6-8 FFs, to have a better chance of getting a clean input.

1.       8. How to solve the glitch of digital circuit??      

Glitch can be smoothened by the using a capacitor from the supply to the ground

(0.01µ and 0.1µ are the commonly used values.....)

9. what is difference between RAM and FIFO? 

FIFO does not have address lines; RAM is used for storage purpose where as fifo is used for synchronization purpose i.e. when two peripherals are working in different clock domains then we will go for fifo.



Design a FIFO 


A synchronous FIFO is a FIFO where the same clock is used for both reading and writing.
An asynchronous FIFO uses different clocks for reading and writing.

Asynchronous FIFOs introduce metastability (it means that it has equilibrium) issues. A common implementation of an asynchronous FIFO uses a Gray code (or any unit distance code) for the read and write pointers to ensure reliable flag generation. One further note concerning flag generation is that one must necessarily use pointer arithmetic to generate flags for asynchronous FIFO implementations. Conversely, one may use either a "leaky bucket" approach or pointer arithmetic to generate flags in synchronous FIFO implementations.

Asynchronous FIFOs required read and write pulses to be generated as data is
moved through the part, and generating these pulses is difficult to do at high speed

Application: It is normally used in network components such as routers, switches, etc. and in electronic circuitry that we use on daily basis such as TVS, radios, MP3 players, etc. As to why not use an ordinary buffer is just not as efficient for today's and future applications.


Synchronous FIFOs have quickly become the FIFOs of choice for new designs. This movement to synchronous FIFOs from their asynchronous predecessors is due mainly to speed and ease of operation. However, there are also many other advantages which these devices bring such as
synchronous flags, programmable almost empty and almost full flags, depth expansion, and retransmit. Synchronous FIFOs are easier to use at high speeds since they can be operated by free running clocks.

In many board to board communication schemes, error checking is done to insure proper transmission. Synchronous FIFOs have a retransmit feature which allows the board which
is sending the data to re-send or “retransmit” the data when an error occurs. Another popular use for FIFOs is interprocessor communication. Often processors run at different bus rates, so passing data through a FIFO allows each processor to burst data into and out of the FIFO at their maximum speeds. FIFOs have no address lines, which saves pin count and therefore board space. Because of this, FIFOs are often used to buffer sequential data such as video or voice. Telecommunication and datacommunication information possesses this sequential ordering as well. Often FIFOs are used on the front end of each network port to synchronize incoming network
packets.

Different duty cycle clock generation
Hold and setup violation condition

Q2: What kinds of timing violations are in a typical timing analysis report? Explain!
Ans: Acceptable answers...
- Setup time violations
- Hold time violations
- Minimum delay
- Maximum delay
- Slack
- External delay

Q3: List the possible techniques to fix a timing violation.
Ans: Acceptable answers...
- Buffering
- Wire sizing
- Transistor sizing
- Re-routing
- Placement updates
- Re-synthesis (logic transformations)
- Cloning
- Taking advantage of useful skew
- Making sure we don't have false violations (false path, etc.)

Blocking and Non-blocking: The Verilog language has two forms of the procedural assignment statement: blocking and non-blocking. The two are distinguished by the = and <= assignment operators. The blocking assignment statement (= operator) acts much like in traditional programming languages. The whole statement is done before control passes on to the next statement. The non-blocking (<= operator) evaluates all the right-hand sides for the current time unit and assigns the left-hand sides at the end of the time unit.


// Section 1: Blocking statements execute sequentially
#5 a = b;  // waits 5 time units, evaluates and applies value to a
   c = d;  // evaluates and applies value to c

// Section 2: Non-Blocking statements execute concurrently
#5 a <= b; // waits 5 time units, evaluates, schedules apply for end of current time
   c <= d; // evaluate, schedules apply for end of current time
           // At end of current time both a and c receive their values

How the following verilog code is synthesized???


reg sel, a;
always @ (sel, a)
  begin : latching_if
    if (sel == 1)
      f = a;
  end
Incomplete Assignment : Now analyze the behaviour of the code. If sel is 1, f gets a. But what happens when sel is 0? Well, very simply, nothing! f does not and can not change. When sel is fixed at 0, we can change a as much as we like, f will not be assigned the value of a. If we suppose that an if statement synthesises to a multiplexer, then we must be able to configure the multiplexer such that f only gets the value of a when sel is 1. This can be achieved by feeding back the multiplexer f output back to the 0 input; in hardware terms this is a transparent latch and this is exactly the hardware synthesized by a synthesis tool given this Verilog code.


If the target architecture does not contain transparent latches the synthesis tool will generate multiplexer circuits that employ combinational feedback in order to mimic the latching behaviour required.
Now, this is very well but what's really happening here? One minute if statements create multiplexers, the next they create latches. Well, it's not the if statements, but the process as a whole that counts. If it is possible to execute an always block without assigning a value to a signal in that always block, the reg variable will be implemented as a transparent latch. This is known as incomplete assignment.


divide by 3.5 clock divider

Divide by 3.5 clock divider

- Divide by 3 first and add the negedge flop in series to make divide by 3.5

A simple divide by 3 counter can be as as follows

=== Divide by 3 ===
always @ (posedge clk or negedge reset)
if (!reset) Q[1:0] <= 2'b0;
else Q[1:0] <= {Q[0], (!Q[1] & !Q[0])};

The above code is a sequence of 00, 01, 10, 00.

always @(negedge clk)
Q0_inv <= Q[0];

assign divide_by_3 = Q[0] | Q0_inv ;

====End of Divide by 3===

always @ (negedge clk)
divide_by_dot5 <= divide_by_3 ;

assign divide_by_3dot5 = divide_by_3 | divide_by_dot5;

===== End of Divide by 3.5====