Digital circuit Timing analysis

Timing analysis is an integral part of ASIC/VLSI design flow. Timing analysis measures the delay along the various timing paths and verifies the performance and operation of the design. Anything else can be compromised but not timing!. 

There are 2 types of timing analysis.

1. Static Timing Analysis (STA)
2. Dynamic Timing Analysis (DTA)

Remember Dynamic Timing Analysis (DTA) and Static Timing Analysis (STA) are not alternatives to each other.

 Static timing analysis is a method of validating the timing performance of a design by checking all possible paths for timing violations under worst-case conditions without requiring simulation. It considers the worst possible delay through each logic element(timing arc), but not the logical operation of the circuit. Static timing analysis checks all the paths in the circuit and even the false paths. False paths are paths that are not possible or interesting in actual operation of the circuit. Therefore you can say that static analysis starts above 100% and works towards 100% by detecting and excluding the false paths.

The basic STA algorithm is linear in runtime with circuit size, allowing analysis of designs in excess of 10 million instances. The basic STA analysis is conservative in the sense that it will over-estimate the delay of long paths in the circuit and under-estimate the delay of short paths in the circuit. This makes the analysis ”safe”, guaranteeing that the design will function at least as fast as predicted and will not suffer from hold-time violations.

The STA algorithms have become fairly mature, addressing critical timing issues such as interconnect analysis, accurate delay modeling, false or multi-cycle paths, etc.
Delay characterization for cell libraries is clearly defined, forms an effective interface between the foundry and the design team, and is readily available. In addition to this, the Static Timing Analysis (STA) does not require input vectors and has a runtime that is linear with the size of the circuit as the Dynamic Timing Analysis (DTA) works with spice models

Static tools have made major advancements in recent years, in fact all synthesis tools use static timing analysis internally. Something good about this approach is that almost all tools using it supports multi-cycle paths, in which a path delay constraint exceeds a single clock period. Everything isn't just good, many static timing tools have problems with feedback loops.

The static timing analyzer will report the following delays: Register to Register delays, Setup times of all external synchronous inputs, Clock to Output delays, Pin to Pin combinational delays. The clock to output delay is usually just reported as simply another pin-to-pin combinational delay. Timing analysis reports are often pessimistic since they use worst case conditions.

Some examples of Static Timing Analysis(STA) tools; 

• Encounter Timing System and Celtic(From cadence), 
• PrimeTime (from Synopsys),
• SST velocity(From Mentor),
• Timecraft (Incentia) &
• Tekton(From Magma-part of Synopsys) . 

Dynamic timing analysis has to be accomplished and functionality of the design must be cleared before the design is subjected to Static Timing Analysis (STA).  Dynamic timing analysis (DTA) analysis uses simulation vectors to verify that the circuit computes accurate results from a given input without any timing violations. Quality of the Dynamic Timing Analysis (DTA) increases with the increase of input test vectors. Increased test vectors increase simulation time. The problem is that the simulations vector not can guarantee 100% coverage. The goal for the dynamic analysis is to get a 100% coverage. Dynamic timing analysis can be used for synchronous as well as asynchronous designs. Static Timing Analysis (STA) can’t run on asynchronous designs and hence Dynamic Timing Analysis (DTA) is the best way to analyze asynchronous designs. Dynamic Timing Analysis (DTA) is also best suitable for designs having clocks crossing multiple domains. As a rule, however, only dynamic timing verification tools support glitch detection and race conditions, since these are inherently dynamic events.

Some examples of Dynamic Timing Analysis (DTA) tools; 

• Modelsim (from mentor Graphics), 
• VCS (from Synopsys) & 
• NC-Sim(from cadence)  

DTA is also carried out on post layout netlist to verify that functionality of the design has not changed. Test vectors remain same for both.

Differences between Dynamic Timing Analysis (DTA)  and Static Timing Analysis (DTA) 

Static Timing Analysis (STA) works with timing models where  the Dynamic Timing Analysis (DTA) works with spice models. The problem associated with DTA is the computational complexity involved in finding the input pattern(s) that produces maximum delay at the output and hence it is slow. Table 1 shows the complete differences between the two analysis..

Table 1 lists out the difference between Dynamic Timing Analysis(DTA) and Static Timing Analysis(STA).