2:1 multiplexer to logic gates implementation

The 2:1 multiplexer allows the selection of one of the 2 samples of input data at a time. 

Figure 1 shows the symbolic representation of 2:1 multiplexer. In case of the multiplexer line A data is chosen when ‘0’ is asserted at S (select line) and B line chosen with the assertion of ‘1’ at S.

Figure 1: Symbolic Representation of 2:1 Multiplexer

Truth table and Karnaugh-map for the 2:1 multiplexer is shown in Figure 2 and Figure 3.

Figure 2: Truth Table of 2:1 Multiplexer

Figure 3: Karnaugh map for 2:1 multiplexer

Boolean equation for the 2:1 multiplexer becomes

Z=AS' + BS ------------------------------------- (1)

1.  NOT gate realization

 When A = 1 and B=0, equation (1) results in Z=S'

Figure 4: Not gate realization with 2:1 Mux

2.  AND gate realization

 When A = 0 , equation (1) results in Z=BS

Figure 5: AND gate realization with 2:1 Mux

When A = S , equation (1) results in Z=AB

Figure 6 : Another possible way of realizing AND gate with 2:1 Mux

3.  OR gate realization

When B=1, equation (1) becomes Z=AS' + S

Above equation also can be written as Z=A+S

Figure 7: OR gate realization with 2:1 Mux

4.  NOR gate realization 

When B=0 and A=A', equation Z=A'S'= (A+S)'

Figure 8 : NOR gate realization with 2:1 Mux

5.  NAND gate realization 

When A=1 and B=B', equation Z=S'+B'S

Above equation also can be written as Z=S'+B' =(SB)'

Figure 9: NAND gate realization with 2:1 Mux

6.  XOR gate realization 

When B=A', equation Z=S'+B'S=A⊕S

Figure 10: XOR gate realization with 2:1 Mux

7.  XNOR gate realization 

When A=B', equation Z=B'S'+BS = BΘS

Figure 11: XNOR gate realization with 2:1 Mux